1. The Field of the Invention
This invention generally relates to the field of wafer level testing and more specifically, to AC and/or DC testing of optoelectronic devices at the wafer level.
2. Related Technology
Optoelectronic devices such as lasers are commonly used in many modern components. One use that has recently become more common is the use of lasers in data networks. Lasers are used in many fiber optic communication systems to transmit digital data on a network. In one exemplary configuration, a laser may be modulated by digital data to produce an optical signal, including periods of light and dark output that represents a binary data stream. In actual practice, the lasers output a high optical output representing binary highs and a lower power optical output representing binary lows. To obtain quick reaction time, the laser is constantly on, but varies from a relatively high optical output to a relatively lower optical output.
One type of optoelectronic device that is used in optical data transmission is a Vertical Cavity Surface Emitting Laser (VCSEL). A VCSEL is typically constructed on a semiconductor wafer such as Gallium Arsenide (GaAs). VCSELs are generally formed as semiconductor diodes. Manufacturers of optoelectronic devices such as VCSELs typically perform various performance tests on the devices before they are delivered to distributors and end customers. This performance testing can be used to detect defects in optoelectronic devices. This performance testing can also be used to sort optoelectronic devices into groups of devices that are suitable for some applications but are not suitable for other applications.
One type of testing that is performed on optoelectronic devices is DC testing. DC testing is used to quantify operational characteristics of the optoelectronic devices when DC currents and voltages, such as bias currents and voltages, are applied to the devices. DC testing can be used to quantify light intensity-current-voltage (LIV) characteristics. DC testing can be performed at the wafer level on devices that have individual top side contacts and a common bottom contact. Nonetheless, even at the wafer level, DC testing for a 3 inch wafer of laser diodes may take a relatively long time, as long as 12 to 14 hours for example.
Another type of testing performed on optoelectronic devices is AC testing. AC testing quantifies the operation characteristics of the optoelectronic devices when AC currents and voltages, such as modulation currents and voltages, are applied to the devices. Commonly, data derived from AC testing is used to generate an eye diagram.
An eye diagram is a graph illustrating, in one example, power output as a result of AC modulation. For example, a constant AC signal, such as a digital square wave at a given frequency, is used to modulate a laser diode. In one example, high values of the digital square wave correspond to logical 1s, while low values of the digital square wave correspond to digital 0s. The power output of the laser diode is then graphed for a half cycle as a function of time. Successive half cycles of the power output are graphed and overlaid on one another. This process provides a visual depiction of the area in which one could expect to find a high (logical 1) or low (logical 0) power output. The eye diagram can be used to quantify characteristics such as rise time, fall time, jitter, and overshoot.
Some optoelectronic devices formed on a wafer share a common bottom contact. In present systems, AC testing for these optoelectronic devices is performed at the device level after the optoelectronic devices have been separated from the wafer. This AC testing is performed at the device level because the capacitance between the individual top contact and the common bottom contact is too large to effectively test high frequency response when each optoelectronic device is tested at the wafer level. In particular, testing at above, for example, 1.5 GHz is difficult, if not impossible, on optoelectronic devices in a wafer where the optoelectronic devices have a common bottom contact and individual top contacts.
Testing at the wafer level can be performed at a much faster rate than testing at the device level. Preparing to test at the wafer level requires a single act of mounting an entire wafer in a test apparatus. Preparing to test at the device level requires that each device to be tested be cut from the wafer, packaged, and mounted in a test apparatus. Because of the amount of time that would be required to individually test every device from a wafer, current methods of device testing have relied on statistical sampling to reduce the amount of AC testing that is done for a wafer batch of devices. This statistical sampling involves testing only a statistically significant percentage of the devices from a wafer, such as 20 out of about 65,000. If a certain percentage, for example 20%, of the sampled devices fail testing, the entire wafer batch of devices is discarded.
Current methods of AC testing can result in wasted resources. If DC testing is performed on the entire wafer prior to a failing AC testing, 12-14 hours of DC testing are wasted in performing the DC testing. Further, while a wafer may include a significant number of working devices, or may contain devices that will meet some customers' specifications while not meeting others, if a certain percentage of the sampled devices fail testing, even the working devices from the wafer are completely discarded.